Recently, particularly along with the increase in the integration and functionality of semiconductor integrated circuits, there has been a demand for development of micro-fabrication techniques for miniaturization and densification. Planarization techniques for interlayer insulating films and embedded wirings are important in semiconductor device production processes, in particular, in the process of forming multilayered wirings. That is, as the multilayered wirings are increasingly formed due to the miniaturization and densification in the semiconductor production processes, the degree of irregularities tends to increase in the surfaces of the individual layers, resulting in a situation where the step height exceeds the depth of focus in lithography. In order to prevent such a problem, high planarization techniques are important in the process of forming multilayered wirings.
As the material for such wirings, Cu has attracted attention because of its lower resistivity compared with conventionally used Al alloys and also because of its excellence in electromigration resistance. Since the vapor pressure of copper chloride gas is low, it is difficult to form Cu into the shape of wirings by Reactive Ion Etching (RIE) which has been conventionally used. Therefore, in order to form the wirings, a Damascene method is used. In this method, concave portions such as trench patterns and via holes for wirings, are formed in an insulating layer. A barrier layer is then formed thereon, and then Cu is deposited so as to be embedded in the trench portions to form a film by sputtering, plating or the like. Subsequently, the excess Cu and barrier layer are removed by Chemical Mechanical Polishing (hereinafter referred to as “CMP”) until the surface of the insulating layer is exposed, other than the concave portions, whereby the surface is planarized to form an embedded metal wiring. Further, it is possible to form multilayered wirings comprising Cu and SiO2 film by depositing an interlayer insulating film comprising SiO2 on an embedded wiring, planarizing the SiO2 film by CMP and forming the next embedded wiring. Recently, a Dual Damascene method has been predominantly used, in which Cu wirings and via holes embedded with Cu are simultaneously formed (e.g. Patent Document 1).
Further, in order to electrically separate devices such as transistors, shallow trench isolation (hereinafter referred to as STI) has been employed. In this method, a trench is formed on a silicon substrate while a device region is masked with a SiNx film, and then a SiO2 film is deposited so that it is embedded in the trench, and then any SiO2 film on the SiNx film is removed by CMP to electrically separate the device region. During CMP, it is common to use the SiNx film as a stopper by letting the removal rate of the SiNx film and the removal rate of the SiO2 film have a selective ratio, so that polishing is terminated at the time when the SiNx film is exposed.
For such formation of Cu embedded wirings, for planarization of the interlayer insulating film, development of a polishing compound which provides a high removal rate of the SiO2 film and a low removal rate of the SiNx film has been developed. Heretofore, as abrasive grains to be used for the above CMP, silica abrasive grains have been commonly used. However, they provide a low selective ratio between the removal rate of the SiNx film and the removal rate of the SiO2 film, cerium oxide (hereinafter referred to as CeO2) abrasive grains excellent in such selective ratio are becoming used instead.
For example, an attempt has been made to use a polishing compound in the form of a slurry containing ultrafine particles of high purity CeO2 for the above process for producing a semiconductor device (e.g. Patent Document 2) However, since CeO2 in a low crystalline state is chemically highly reactive, when a polishing compound slurry containing such CeO2 ultrafine particles is used, problems such as a burned spot, orange peel and deposition on the polished surface tend to arise, and thus they cannot be used for precision polishing. In order to solve these problems, an attempt has been made is to use CeO2 ultrafine particles obtained by mixing, with stirring, an aqueous solution of cerous nitrate with a base in such a mixing ratio that the pH value of the mixture ranges from 5 to 10, followed by aging at from 70 to 100° C. (Patent Document 3).
However, in this method, it is not easy to set the reaction conditions, and it is hard to control the end point of the reaction, and accordingly, it is difficult to control the particle size of the fine particles and the particle size distribution, and no sufficient properties were achieved for use as a precision polishing slurry in the process for producing a semiconductor device.
On the other hand, Patent Document 4 discloses a method for producing a magnetoplumbite type ferrite (MFe12O19) powder by glass crystallization method, comprising subjecting glass to heat treatment at a temperature of at least the glass transition point to precipitate ceramic crystals in the glass matrix, and dissolving and removing the glass with a weak acid to separate only precipitated crystals. This glass crystallization method is characterized in that it is effective as a means for preparing high purity ceramic particles and that the particle size, the particle size distribution and the shape of the particles are easily controlled, in a case where substances other than the crystallized particles are completely removed.
Patent Document 1: JP-A-2004-55861
Patent Document 2: JP-A-8-134435
Patent Document 3: U.S.P. 5,938,837
Patent Document 4: U.S.P. 4,569,775